In order to sample and process an electronic signal, the phase of that signal is first determined. When a serial electronic device, such as a pager, receives a signal, the phase of that signal is not known. Thus there must be a mechanism for determining the phase before sampling and processing.
As shown in FIGS. 1 and 2, in the prior art, an analog receiver 20 listens for an analog input signal sent from a transmitter 22. Specifically, it waits for a trigger, such as a transition from no signal to a signal (200). The receiver 20 then converts the analog signal to a digital signal for sampling (202). An over-sampler 24 then samples the data using multiple clocks 26, producing four sampled signals 28 (204). Here, the clocks are generated by a voltage controlled oscillator 30 and are clocks of the same frequency and four different phases. One of the four clocks will be optimal for sampling the data, as compared to the other three clocks.
An edge detector 32 analyzes the four sampled signals 28. The edge detector 32 detects transitions between digital logic levels (206). Hence it will detect that a sampled signal is the result of a sampling clock sampling the data when it was transitioning from low to high, or from high to low. The results of the edge detector 32 are sent to a decision matrix 34. The decision matrix 34 determines which clock has sampled a transition from low to high and which clock has sampled a transition from high to low (208). The clock whose phase is between the phases of those two clocks is sampling the data roughly at the midpoint of the data pulse (210). Thus, that clock is sampling the data better than any of the others. Data is then sampled by that clock.
The transmitter 22 and receiver 20, however, are independent of one another, and use different clocks. Even if those clocks are intended to be identical in frequency, subtle differences will materialize over time. Take, for example, an external device, such as a CD-ROM player, connected to a personal computer. The CD-ROM player transmits data to a receiver on the personal computer. The CD-ROM player's clock is independent from the personal computer's clock. FIG. 3(a) shows one of the clock phases 40 aligned with the center of the data pulse 42. Although an optimal sampling clock was initially chosen as described above, after a period of time, clock differences can become large enough to make a different clock optimal. FIG. 3(b) shows a different clock 44 sampling the data in the center of the pulse 42.
Because the decision matrix 34 also experiences drift and jitter, the decision matrix 34 may not be able to determine whether a sampling clock of increasing or decreasing phase is now the optimal sampling clock. Furthermore, as the speed of serial communication increases, the bit error rate (“BER”), or the rate at which data is incorrectly sampled, becomes a greater concern.